Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to excess voltage events. It is well known that SC devices and ICs can be exposed to excess voltage during handling by humans or machines or other circumstances. These occurrences are often referred to in the art as electrostatic discharge (ESD) events. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's. As used herein, the term “integrated circuit” and the abbreviation IC are intended to be interpreted broadly and include any form of multi-element electronic circuit that may be exposed to ESD events and not be limited to those formed on or in a monolithic semiconductor substrate.
FIG. 1 is a simplified schematic diagram of circuit 20 wherein ESD clamp 21 is placed between input-output (I/O) terminal 22 and ground or common terminal 23 of an IC to protect other devices or elements therein, that is, to protect circuit core 24, coupled to the I/O and common terminals 22, 23. Circuit core 24 may contain any type or combination of electronic elements. FIG. 2 is a simplified schematic diagram illustrating internal components of ESD clamp 21, utilizing, for example, bipolar transistor 25, having emitter 26, collector 27, base 28, resistance 29 and Zener diode 30 having terminals 301, 302. When the voltage across terminals 22, 23 rises beyond a predetermined limit, Zener diode 30 turns on, thereby switching transistor 25 into conduction and clamping the voltage across terminals 22, 23 at a level below that capable of damaging circuit core 24.
FIG. 3 shows simplified cross-sectional view 32 of ESD clamp 31 implementing ESD clamp 21 of FIGS. 1-2 in semiconductor substrate 37, according to the prior art. ESD clamp 31 comprises N-type buried layer (NBL) 34, above which lies P-type layer or region 36. P-well region 38 extends from surface 35 into P region 36. N-type sinkers 40 extend from surface 35 to make ohmic electrical contact to NBL 34. N+ regions 42 make ohmic contact to N-type sinkers 40. P+ regions 43 and 45 make ohmic contact to P-well 38. P-well 38 serves as the base of transistor 25 (see FIG. 2). N+ region 44 serves as the emitter of transistor 25. P+ region 45 serves as anode 301 of Zener diode 30 (see FIG. 2) whose cathode 302 is provided by N-type sinker 40 and N+ contact 42. Zener space charge region (abbreviated as “ZSC”) 39 is located between P+ region 45, and N-sinker 40 with N+ contact 42. Anode terminal 22 of ESD clamp 31 is coupled to N+ region 42 and cathode terminal 23 of ESD clamp 31 is coupled to N+ region 44. Conventional passivation layer 37 is provided on surface 35.
While such prior art devices are widely used as ESD clamps, they suffer from a number of limitations. Typical limitations are illustrated, for example, in FIG. 4. FIG. 4 shows plot 46 of the current in milliamps between terminals 22, 23 of ESD clamp 31 as a function of the voltage in Volts across terminals 22, 23 for nominally identical clamps, 311, 312, 313, 314, etc., (collectively 31) located in different regions of and orientations on the same IC, and fabricated at the same time using the same mask set and processing steps. It is observed that some of the ESD clamps (e.g., ESD clamps 311, 312) have clamp voltages at 5 milliamps of about 11-12 volts while others on the same chip (e.g., 314) show clamp voltages at 5 milliamps of about 19 volts. This is observed even though ESD clamps 311, 312, 313, 314, etc., are manufactured at the same time using the same mask set on the same substrate and the same processing steps, and would ordinarily be expected to exhibit nearly identical properties no matter where they are located on the IC chip. This variability is undesirable since it can expose some I/O terminals and their associated circuit cores to significantly larger ESD voltages than other parts of the overall IC.
Accordingly, there is an ongoing need to provide improved ESD clamps, especially ESD clamps that operate at more consistent voltages independent of their location and/or orientation in a particular IC. Further, it is desirable that the improved ESD clamps be obtainable without substantial modification of the manufacturing process used for forming the clamps and their associated circuit core of the IC. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.